1. Field of the Invention
The present invention relates to a serial clock generator, and more specifically to serial clock generating circuit for use in a serial data transfer circuit include in data processing systems including microcomputers.
2. Description of Related Art
Conventionally, a serial data transfer circuit, which is one of various perheral hardwares of data processing systems, has been widely used in comparison with a parallel interface utilizing a bus connection, because the number of signal lines required for interfacing is small and therefore is economic, and because of other reasons.
On the other hand, data processing systems have been required to communicate with various peripheral devices and other data processing systems. However, serial transfer rates being used are different dependently upon the devices and the systems. Therefore, a serial data transfer circuit included in the data processing system has been desired to easily deal with serial transfer rates of a wide extent, for example by a software processing with a central processing unit.
Furthermore, in a serial transfer system in which an interface signal line does not include a clock line for synchronizing transmission and receipt of the transfer data, a receiving side of the serial data transfer is requiring to have a circuit for generating a serial clock for receiving a transmitted data.
The serial clock generating circuit provided at the receiving side of the serial data transfer has been adapted to receive a basic clock having a frequency N times (for example, 16 times or 32 times) of a serial transfer rate which is previously determined in accordance with a Protocol, and to frequency-dividing the basic clock by N so as to generate an internal clock having the same period as that of the serial transfer rate. In addition, the internal clock is phase-adjusted to become in phase with a signal level transition of the received serial data.
This phase-matching of the internal clock with the received serial data is ceaselessly performed at each signal level transition on a serial data transfer signel line. The reason for this is that even if the phase-matching has been realized, a phase-mismatching will occur between a serial clock of the transmission side and a serial clock of the receiving side due to various causes such a delay of a transfer path and a change of temperature of environment.
As mentioned hereinbefore, in the serial transfer system in which an interface signal line does not include a clock line for synchronizing transmission and receipt of the transfer data, and a receiving side of the serial data transfer is required to have a circuit for generating an internal serial clock for receiving a transmitted data, the serial clock generating circuit used at the receiving side detects the signal level transition on a receiving serial data line and synchronize the phase of the internal serial clock. Therefore, the serial clock generating circuit deals with only a serial data transfer in accordance with a protocol in which transfer control procedure and a code transfer system for a serial data transfer are determined in such a manner that a signal level on a receiving data signal line will change without exception within a constant period allowed in the transfer system. One example of the protocol is the Non-Return-to-Zero-Invert format (NRZI format) of Japanese Industrial Standard JIS C 6363-1978 to 6365-1978: High level Data Link Control Procedure.
A conventional serial clock generating circuit capable of dealing with the above mentioned serial data transfer could have adjusted the internal serial clock into phase to the signal level transition even if the transfer timing of the serial data transfer accidentially changes. However, the conventional serial clock generation circuit has been such that an output signal of a binary counter having a fixed bit length is used for generation of an internal serial clock. Therefore, conventional serial clock generation circuit could not generate an internal serial clock corresponding to any serial data transfer rate used in a necessary data transfer, on basis of a count clock generated a single quartz-crystal oscillator. In other words, if a count clock is fixed by the quartz-crystal oscillator being used, the serial clock generated also becomes fixed. In addition, it is not easy to modify the circuit so that the bit length and the count number can be changed in a software manner.
Therefore, in the case that a data processing system has to be capable of dealing with a plurality of serial data transfers having different transfer rates, (1) there have been provided a plurality of quartz-crystal oscillators so that one of the quartz-crystal oscillators is selected in a software manner so as to supply a required count clock to the serial clock generating circuit, or (2) there is provided a frequency-division circuit receiving a clock generated by a single quartz-crystal oscillator and for generating in a software manner a count clock in accordance with each of different serial transfer rates, the count clock thus generated being supplied to the serial clock generating circuit.
However, the provision of the plurality of quartz-crystal oscillators will results in an increased number of parts in an application system, and hence, in an increased cost of the application system.
In the case of the software-controlled frequency-division circuit provided in addition to the serial clock generating circuit, on the other hand, there must be used a quartz-crystal oscillator having an oscillation frequency of as high as possible, in order to ensure that the serial clock generating circuit can generate a plurality of serial clocks having arbitrary different frequencies without decreasing a resolution of the serial clock generating circuit, since an ordinary frequency-division circuit is composed of a binary counter. However, it can ordinarily be said that the higher the oscillation frequency becomes, the expensive the quartz-crystal becomes, and the larger the power consumption of the circuit becomes.